This invention relates generally to digital computers, and more particularly, to the generation of memory addresses for use by computers. A typical computer system includes a central processor and at least one random access memory module. In general, the central processor has access to both a program memory, in which programs of instructions are stored, and a data memory in which data required for operation of the programs are stored. Of course, the computer system will have other components as well, such as input and output devices.
In the processing of data, a computer system must frequently and repeatedly compute data memory addresses for the storage and retrieval of the data. A typical sequence of operations may call for the sequential retrieval of a set of data stored in consecutive addresses in the data memory. A common technique for handling this in a general-purpose computer is to employ "indexed" addressing, whereby the address from which a stored item is to be retrieved is computed by adding a base address to a number stored in an index register. The index register is then incremented or decremented after each retrieval step in the sequence. Thus, for example, if the first address to be accessed is A, the base address, which can be part of a retrieval or "load" instruction, would also be A, and the index register can be set initially to zero. After the first access to memory, the index is incremented to "1" and the next access would be to address A+1, and so forth. The program of instructions for this sequence must include an instruction to increment the index register after each retrieval, and another to test the value of the index register to determine if the end of the sequence has been reached.
Since a test for a non-zero value of the index register may be cumbersome, the program may instead be designed to store in the index register an initial a count of items to be accessed, and then to decrement the index register during each cycle, testing for a zero value to determine the end of the sequence.
In any event, it will be appreciated from this simple example that the central processor must execute a number of instructions of a "house-keeping" nature to compute the appropriate memory addresses for a particular data-processing problem. For relatively complex data-processing problems, in which the data may consist not of simple one-dimensional arrays, but may instead take the form of multi-dimensional arrays or unusual configurations of data, the central processor may spend a substantial proportion of its available time merely in computing memory addresses.
This problem is further compounded if the central processor is called upon to manipulate, at about the same time, several different sets of data having different organizations. Indexes and pointers relating to one set of data may have to be temporarily saved while the indexes and pointers relating to another set of data are being employed. The computational overhead that these manipulations impose on the computer system become increasingly significant as the complexity of the computer applications increases. A related difficulty is that the complexity of the programming task also increases, so that the cost of the resulting software is significantly higher.
It will be appreciated from the foregoing that there is a need for an alternative to the generation of memory addresses by the central processor. The present invention fulfills this need.